The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling-down also produces a relatively high power dissipation value, which may be addressed by using low power dissipation devices such as complementary metal-oxide-semiconductor (CMOS) devices. CMOS devices have typically been formed with a gate oxide and polysilicon gate electrode. There has been a desire to replace the gate oxide and polysilicon gate electrode with a high-k gate dielectric and metal gate electrode to improve device performance as feature sizes continue to decrease. However, problems arise when integrating a high-k/metal gate feature in a CMOS process flow due to various factors such as the gate trench width used in replaced polysilicon gate (RPG), Lg ˜25.5 nm, devices is very narrow (e.g., <10 nm for N-MOS and <2 nm for P-MOS). Such a narrow trench may include a bridging across an upper portion of the trench. In other words, the space for wetting the gate metal fill (e.g., Al-fill) is very narrow. Accordingly, the bridging may cause the metal gate fill metal to have voids after being filled into the trench.
Accordingly, an improved metal gate fill and method of making is desired.